1. Field of the Invention
The present invention generally relates to semiconductor memories and, more particularly, to data input circuits for random access memories and especially for synchronous dynamic random access memory write timing.
2. Background Description
Synchronous Dynamic Random Access Memory (SDRAM) chips are well known. Essentially, a state of the art SDRAM, is accessed by providing an initial memory location or address that identifies a first data access location in a string of serially accessed contiguous locations. The first address is known as the burst starting address and the data string is known as the burst or data burst. The burst may have a width, which may be 1 bit, 4 bits or 8 or more bits, and a length that may be 2, 4, 8 or more locations. Burst width and length are set at the SDRAM architecture designer's discretion and the result of numerous design trade offs. Internally to the SDRAM, during any particular access, all of the cells in the burst are accessed simultaneously in parallel and serialized for external burst transfers.
This serial external data transfer and parallel internal data transfer is also typically referred to as "data prefetch." Thus, data is passed to or retrieved from the chip serially, i.e., externally, and data passed to the chip may then be written to the array in parallel or read from the array in parallel to be passed off chip serially. Using data prefetch reduces the number of external data lines, which decreases chip area. Also, prefetch allows accessing the array at a significantly lower frequency than the external data rate.
FIG. 1 shows a write driver circuit 100 for a prior art SDRAM. The write driver 100 is typically included in a sense amplifier for writing input data 102 to a memory array 103. A receiver 104 passes the input data when the receiver enable 106 is asserted. A latch 108 temporarily stores the data from the receiver 104. The latched data is passed to the input of write driver 110. When write enable 112 is asserted, write driver 110 passes the latched data to the memory array 103 for storage at a selected memory location. This approach is adequate when every data bit presented to the input is to be stored in the memory array 103.
As SDRAM performance objectives and operating frequency are pushed, increasingly, there is a need to prefetch 2 or more data bits. Increasing the number of prefetch bits produces an effective external operating frequency that is independent of the array operating frequency. However, existing prefetch architectures merely replicate both the inputs and the write drivers for the number of pre-fetched bits. This approach increases the number of data busses and its associated bus area, which in turn results in a larger SDRAM chip.
Thus, there is a need for a improving SDRAM write performance without increasing SDRAM chip size.